Introduction

As the demand for semiconductor products/services continues to grow along with the exponential rise in consumer expectations, the semiconductor industry is witnessing a wider range of technological innovations. Foundries are moving toward lower geometries (FinFET 7nm, 5nm etc.) for fabricating SOC/ASIC to support latest generation gadgets/instruments. While one of the leading foundries started with 7FF evolving to second-generation N7+ before launching the 5nm process, As per information Samsung is confident on 7LPP while Global Foundries gave up 7nm work. The key Drivers behind this trend are the benefits in terms of power, performance and other features that become possible with lower geometries.

What is 7nm?

1. 7nm refers to a technology node that is one of the most advanced FinFET process nodes used in chip design & fabrication
2. 7nm is one of the latest process nodes in production today that provides shrink down transistors, offering improvement in silicon area utilization and power efficiency, which is going on into production mode for the last couple of months.
3. The tradeoff is increase in chip design & manufacturing process complexity, along with higher manufacturing/fabrication cost.

Benefits of 7nm Technology

The main benefits are PPA i.e. power, performance and area, which is the main ask of the Mobile, handheld device and processor industry. It is evident from the fact that Apple recently announced their A13 Bionic chip used in the iPhone 11 built using TSMC's 2nd gen 7nm process, while Qualcomm is already shipping their snapdragon parts in 7nm.

• Reduced power consumption -This is a key parameter for the mobile/handheld industry, for which the power consumption & battery life is a primary concern to address. Per published data, 7nm TSMC process gives 40% power saving over 10nm **.
• Improvement in switching performance - This is equally important in server applications and smartphones, which use faster processors and want to add more threads to their multi-tasking capabilities. Faster switching means faster application run time. Per the data published by TSMC, this shows 20% speed improvement**.
• 1.6x higher density - This is a key advantage to produce the lightest and thinnest possible smartphones (that is having a small form factor). Per published data, TSMC 7nm has resulted in area saving because of 1.6X logic density vis-a-vis 10nm **.

Challenges of 7nm Technology

From the second half of 2016, when serious efforts started in designing and manufacturing of chips in 7nm, the Industry realized that there would be a substantial increase in fab cost for lower geometries along with challenges to meet the Yield number and consistency in process parameters.

• The fundamental question with silicon transistors is that, at 7nm point, the transistors sit so close to each other that after you try to shrink further (5nm &3nm) an effect called quantum tunneling will come into the picture. This effect unfortunately means that the transistor cannot be turned off reliably and for the most part, will stay on. So, the physical limitations of silicon are very real and, in fact, create steep challenges to handle it. This necessitates close monitoring of the manufacturing process and the process curve.

Thus all the parameters and their behavior need to be closely monitored. This has been a big challenge for foundries.

• Die Manufacturing -Fabricating transistors is one process, generally called front-end-of- line (FEOL) process. For all the interconnections, back-end-of-line process is used, and this brings the complex part of managing resistance-capacitance. There are local interconnects at the device level, accomplished by middle-of-line process. Global interconnects are done by back-end-of-line and are prone to resistance-capacitance delays. Normally, at lower nodes, back-end-of-line uses multiple patterning, which calls for extra deposition and etching with every pattern, thus increasing the cost of production.
• Logically, multiple patterning can still be used for 7nm. However, the industry is heading toward extreme ultraviolet (EUV) lithography for lower technology nodes. With EUV, back-end-of-line process can be done with single exposure and throughput can be as good as ~1,000 wafers per day.
• Standard architecture of high-performance digital SOCs assumes that all the transistors fabricated in a die work reliably, and we are hereby referring to products that would contain several billion transistors each. This points to the challenge that the Semiconductor design and manufacturing houses have in hand. Thus, manufacturing and reliability of integrated semiconductor devices are crossing all the barriers and reliably producing them is as big a On the other hand, to be profitable, one needs to have yield high enough to cover the manufacturing costs at a reasonable price point.
• Generally, all semiconductor wafers in the current time zone are using photolithography for patterning, based on a light source with a wavelength of 193nm. Manufacturing processes have relied on pattern features down to one-twentieth of the free-space wavelength of light, including immersion lithography, optical phase control, exotic photochemistry and multiple patterning. It is time to switch to a new light source of 13.5nm wavelength, which is the so-called EUV. However, changing to this new wavelength and therefore new processing technology and procedures opens up new challenges for designers too. There are changes to the set of DFM rules given by the foundry, to be followed by designers, in order to ensure their design can be manufactured.
• Testing of Manufactured SOC - Testing of each SOC post fabrication is done on Automatic Test equipment. Quality of testing defines yield and DPPM, and has finite impact on the bottom line or revenue margins. Thus, proper DFT logic is inserted and low power testing techniques are employed to keep yield /DPPM in control. When the first 7nm device came for testing, like all new nodes, it posed challenges in yield and DPPM number, resulting in the design and testing teams tweaking their process to ensure the industry gets double digit yield with an acceptable DPPM number.

Conclusion

Despite all these challenges, the PPA (power, performance and area) has forced major semiconductor giants, especially those in supply chains of cellphone, handheld & server processors to move to 7nm. Qualcomm, AMD, ARM, Apple etc. have declared products in the 7nm space. In fact, some of them after successfully doing designs in 7nm have already started working on the 5nm design process. Therefore, it is evident that the above-mentioned trends are prevalent with major foundries, including further improvising the current 7nm process, asking fabless semiconductor companies to move designs to 5nm and in parallel, working to prove 5nm technology node, along with planning for 3nm.

Reference

*https://www.tsmc.com/english/dedicatedFoundry/technology/logic.htm

**https://www.tsmc.com/english/dedicatedFoundry/technology/logic.htm#l_7nm_technology