Abstract
Synchronous Optical Network / Synchronous Digital Hierarchy (SONET/SDH) and optical fiber have dominated the technology-scenario for building large-scale, high-speed, Internet Protocol (IP)-based networks. The high-bandwidth capacity available for transporting data is the major reason for its explosive use in the Internet and large enterprise data networks.

The problem with conventional networks, when conversion happens to ATM (IP-over-ATM) is the overhead imposed by ATM cell headers (5-bytes out of every 53-bytes), sometimes referred to as the cell tax. Additional overhead is added by AAL5 (padding, 8-byte trailer). IP achieves only about 80 percent of the available line rate when operating over ATM.

This paper describes the Packet over SONET/SDH (POS) technology and Wipro's FPGA core implementing a SONET/SDH to POS mapper. It is addressed to engineering managers who wish to add the Packet Over SONET/SDH Interface to their product range. Wipro's FPGA core and engineering skills could be leveraged for arriving at a cost effective, early-to-market solution for POS.

Authors Ravishankar K Jinu Koshy

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