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Abstract
With the advent of the System On a Chip (SoC) and mass
production of these complex ICs, design of an ASIC with
testability features in it has become a mandatory requirement.
Testability requirements are present in various levels
of an SoC. The internal gates of the chip should be
made testable for stuck-at faults. Internal hard-macros
need to be tested for manufacturing defects. The connection
of the pads with the external pins are to be tested
for bonding faults. Chips placed on boards are to be
tested for the pin connection integrity on the board.
Different methods are used to test each of these defects.
This paper discusses various design / implementation
issues typically need to be consid-ered for designing
a circuitry for testability, achieving high test coverage
in less test time. WIPRO’s synthesizable core for
OHCI (Open Host Controller Interface) over IEEE 1394
Link layer implementation is used as a reference in
this paper.
Author
Sukalyan Mukherjee
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