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Abstract
Conventionally, ASIC design involved development of
medium complexity Integrated Circuits (of less than
500,000 gates). These had a cycle time of roughly 6
months, were processed with 0.35u technology, and were
essentially made up of core logic and some hard macros,
like on-chip SRAMs.
With rapid advances in semiconductor processing technologies,
the density of gates on the die increased in line with
what Moore's law predicted. This helped in the realization
of more complicated designs on the same IC. Over the
last few years, with the advent of bleeding edge technology
applications like HDTV and 3rd generation mobile devices,
an increasingly evident need has been that of incorporating
the traditional microprocessor, memories and peripherals
-or in other words the whole system - on a single silicon.
This is what has marked the beginning of the SoC era.
Research agency In-Stat predicts robust market growth
for SoCs, estimating that volumes will increase an average
of 31% a year. Paradoxically today, the emergence of
system-on-chip technology has brought with it a whole
spectrum of opportunities and challenges. Opportunities
come in the form of drastic reduction in the overall
cycle time of the system with superior performance levels;
challenges are the result of deep sub-micron complexities,
testability issues and time-to-market pressures.
This paper attempts to confront these opportunities
and challenges, and evolve a strategy that can successfully
realize an SoC from concept to silicon. The five key
aspects of a successful design strategy discussed here
are - Architectural strategy, Validation strategy, DFT
Strategy, Synthesis & Backend strategy, and Integration
strategy.
Authors
Udaya Kamath, Rajita Kaundin
To know more about Wipro in consumer electronics, go
to www.wipro.com/consumerelectronics/
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