Abstract
The integrity of Power Distribution Systems (PDS) is becoming very critical as the clock frequencies and power consumption of high-end ASICs/microprocessors continue to increase rapidly. In fact, as more functionality is integrated into modern ASICs and high-end microprocessors, they are consuming increasingly more power than ever before. This fact, coupled with faster operating frequencies and shorter clock edge rates, make the design of PDS ever more challenging. Moreover, as the core supply voltages are lowered to around a volt and half, only very small percentage of ripple on the Power Supply voltages can be tolerated

Author
Vishnu Jwalapuram

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