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Abstract
Lack of co-relation between expected circuit performance
from library characterization values and actual silicon
behavior is getting more critical with the blame being
put on process variation, variable IR drop , temperature
and voltage variation. This is due to multiple reasons
that are been discussed now a days in the industry including
deep sub micron issues , power distribution, variation
in manufacturing process etc. Thus more emphasis is
now on the EDA tools capability to model and analyze
the above issues.
With the Abstract
SoC design typically requires integration of multiple
tool flows and methodologies that aid in realization
of design goal. Integration of flows require standard
interface with reference to makeflow rule files, scripts
and tool control/configuration files. The clarity on
the infrastructure/ flow leads to early adoption of
new tools/features offering flexibility to enable changes
for new technology libraries and tool versions.
This white paper discusses how to simplify flow design
to manage tool integrations with reference to commercial
tools from Verisity, Mentor, Synopsys etc. for front-end
design. Approach for custom scripts that could be developed
to integrate the tools seamlessly in to the flow is
explained. Various teams follow unique methods to handle
this subject. However the requirements could be broadly
classified as described in this paper.
Authors
Pitchumani Guruswamy
Henry Kwan
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